1. Field of the Invention
The present invention relates to a semiconductor device and a layout method and design program thereof, and particularly to a semiconductor device, in which signal lines and power supply lines each formed on different wiring layers are connected by via conductors, and a layout method and design program thereof.
2. Description of Related Art
A plurality of wiring layers are provided in a semiconductor device. A large number of signal lines and power supply lines are formed on each wiring layer. Each of the signal lines and power supply lines provided on different wiring layers are connected by via conductors provided so as to pass through interlayer insulating films located between the wiring layers (See Japanese PCT National Publication No. 2005-535118, Japanese Patent Application Laid-open No. 2005-302756, Japanese Patent Application Laid-open No. 2006-108406, and Japanese Patent Application Laid-open No. 2001-127162). For example, Japanese PCT National Publication No. 2005-535118 discloses a wiring layer on which a plurality of conductive lines extend in an X-direction, and another wiring layer on which a plurality of conductive lines extend in a Y-direction. On each wiring layer, signal lines and power supply lines are alternately disposed. According to the layout described above, the power supply lines are provided so as to form a meshed pattern. Therefore, the power supply lines having the meshed pattern function as a shield for the signal lines. The width of the signal lines and the power supply line is set so as to cover a via conductor. Therefore, the line-and-space L/S or first wiring pitch of the conductive lines where the via conductor exists takes a larger value than the line-and-space L/S or second wiring pitch of the conductive line where the via conductor does not exist. This is because a certain size of margin is necessary between an edge of a via conductor and an edge of a conductive line to keep the via conductor from falling off the conductive line.
However, in the semiconductor device disclosed in Japanese PCT National Publication No. 2005-535118, a via conductor connecting signal lines together, and a via conductor connecting power supply lines with a shielding function together, are formed under the same conditions. Therefore, if each via conductor is so designed as to have a minimum diameter that can be formed, defects may appear in the via conductors, resulting in a higher rate of bad connections in the signal lines. On one hand, if the via conductors are so designed as to be larger in diameter to prevent such bad connections, it is inevitable that both wiring pitches, i.e. the pitch of a lower wiring layer and the wiring pitch of an upper layer, are further increased, resulting in an increase in the area of a semiconductor chip. On the other hand, if two via conductors with a minimum diameter are disposed per a connecting point, it is inevitable, as in the above case, that the wiring pitches are further increased, resulting in an increase in the area of a semiconductor chip. That is, achieving the shielding function, as well as preventing the electrical disconnection or higher resistance of signal lines due to poor contact or higher resistance of via conductors, leads to an increase in an occupied area for a plurality of wiring pattern regions.